This relates to integrated circuits and, more particularly, to performing register retiming on an integrated circuit design.
Every transition from one technology node to the next has resulted in smaller transistor geometries and thus potentially more functionality implemented per unit area on an integrated circuit die. Synchronous integrated circuits have further benefited from this development as evidenced by reduced interconnect and cell delays, which have led to performance increases.
To further increase the performance, solutions such as register retiming have been proposed, where registers are moved among portions of combinational logic, thereby achieving a more balanced distribution of delays between registers, and thus the integrated circuit may be operated at a potentially higher clock frequency.
The registers are typically implemented using clock-edge-triggered latches commonly known as digital flip-flops. Conventional flip-flops only include a data input terminal, a data output terminal, and a clock terminal. Modern flip-flops, however, can have one or more secondary signals including a clock enable terminal, a synchronous clear terminal, an asynchronous clear terminal, a synchronous data terminal, a synchronous load terminal, etc. Since most retiming algorithms are only designed to work with conventional (simple) flip-flops, these complex flip-flops with one or more secondary signals have to be modeled using a simple flip-flop along with additional gate-level combinational logic.
For example, consider a scenario in which an original circuit design includes a first combinational logic block implemented using a first lookup table (LUT), a second combinational logic block implemented using a second LUT, a third combinational logic block implemented using a third LUT, a first flip-flop coupled between an output of the first LUT and an input of the second LUT, and a second flip-flop coupled between the output of the first LUT and an input of the third LUT. In particular, the first flip-flop has two secondary signals, whereas the second flip-flop has only one secondary signal.
In this scenario, a complete modeling of the first complex flip-flop followed by a backward retiming operation may introduce a fourth LUT and four simple flip-flops. Similarly, a complete modeling of the second complex flip-flop followed by a backward retiming may introduce a fifth LUT and three simple flip-flops. As shown in this example, the retimed circuit will include at least two additional LUTs and five additional flip-flops. The number of additional LUTs and flip-flops will generally depend on which secondary signals are being modeled. A retiming operation of a circuit that includes complex flip-flops having secondary signals therefore often results in huge area penalties that cannot be undone.
It is within this context that the embodiments herein arise.